Conventionally, the formation of metal interconnects within an integrated circuit requires a distinct deposition of an etch-stop layer on top of an ILD/metal interconnect layer before a subsequent level of interconnect is processed. For example, FIG. 1 illustrates a metal interconnect formed according to a conventional technique. Referring to FIG. 1, an interlayer dielectric (ILD) 102 is deposited on an etch-stop layer 104, typically silicon nitride. A via 106 and trench 107 are patterned into the ILD 102 according to well-known dual damascene techniques. A barrier layer 108 may be formed on the bottom and sidewalls of the via 106 and the trench 107. The via 106 and trench 107 are then filled with an electrically conductive material, such as copper and planarized to the top of the ILD 102, thus forming a copper interconnect 110. An etch-stop layer 112, is deposited over the planarized ILD 102, the planarized barrier layer 108, and the planarized interconnect 110. Consequently, a second ILD 114, second barrier layer 118, and second interconnect 116 may be formed, the second barrier layer 118 and second interconnect 116 connecting to the first interconnect 110 to provide electrical connection between interconnects 110 and 116. The process may repeat itself for additional ILD/interconnect layers.
The typical method, however, suffers from problems. For instance, the deposition of the etch-stop layer 112 must be performed before subsequent ILD layers can be formed and patterned. The deposition of the etch-stop layer, however, is time consuming and costly because specialized equipment must be used to deposit a traditional nitride or oxide material. Furthermore, the etch-stop layer 112 is a dielectric material typically formed very thick, usually between 30 to 150 nanometers, which significantly adds to the dielectric value of the circuit. The dielectric value is closely tied to the RC response of the circuit. Therefore, the etch-stop layer 112 significantly increases the overall RC delay of the circuit.
Additionally, the etch-stop layer 112, typically silicon nitride, does not inhibit interfacial diffusion of metal, such as copper, effectively at the top 120 of the interconnect along the interface between the etch-stop layer 112 and the interconnect material 110. Interfacial diffusion has been identified as the primary cause of premature electromigration failure.
Some attempts have been made to try and cap the top of the metal interconnect, however these approaches require a very selective process wherein a capping metal can only be deposited onto the metal interconnect, but not onto the ILD. In addition, a separate etch-stop deposition is needed for unlanded via design rules.